This invention relates to a compound semiconductor and, more particularly, to a compound semiconductor device having an etching stopper layer between an active layer and an ohmic electrode.
A heterojunction metal-semiconductor field effect transistor is a typical example of the compound semiconductor device. The high electron mobility transistor is a kind of heterojunction metal-semiconductor field effect transistor, and is featured by an inversion layer at the boundary between an electron supply layer and a channel layer. The heterojunction metal-semiconductor field effect transistor finds a wide variety of application such as, for example, a DBS ( Direct Broadcasting Satellite). The compound semiconductor device is expected to have low-noise characteristics and achieve a high-gain.
In order to enhance the mutual conductance, it is known to increase the dopant impurity in the electron supply layer. Reduction of source resistance is also appropriate. However, when the dopant concentration is uniformly increased in the electron supply layer, a problem is encountered in the hetero-junction metal-semiconductor field effect transistor in low withstand voltage between the gate electrode and the electron supply layer.
A stepped doping concentration structure has been proposed. When the stepped dopant concentration structure is applied to the electron supply layer, the electron supply layer has a relatively heavy dopant concentration close to the channel layer and a relatively light dopant concentration close to the gate electrode.
FIG. 1 illustrates the prior art high electron mobility transistor with the stepped dopant concentration structure. The prior art high electron mobility transistor is fabricated on a semi-insulating substrate 1, which is formed of gallium arsenide. The prior art high electron mobility transistor comprises a buffer layer 2, a channel layer 3, an electron supply layer 4/5, cap layers 8, ohmic electrodes 9 and a gate electrode 10. Gallium arsenide is epitaxially grown on the semi-insulating substrate 1, and forms a gallium arsenide layer. The gallium arsenide layer serves as the buffer layer 2. On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer 3. Heavily-doped n-type aluminum gallium arsenide, i.e., n+Al0.2Ga0.8As and lightly-doped n-type aluminum gallium arsenide, i.e., nxe2x88x92Al0.2Ga0.8As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly-doped n-type aluminum gallium arsenide layer 5. The dopant concentration is 4xc3x9710xe2x88x9218/cm3 (4andtimes; 10xe2x88x9218/cm3) in the heavily-doped n-type aluminum gallium arsenide layer 4 and 1xc3x971017/cm3 in the lightly-doped n-type aluminum gallium arsenide layer 5. The heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5 form in combination the electron supply layer 4/5. The heavily-doped n-type aluminum gallium arsenide layer 4 is contiguous to the channel layer 3, and the gate electrode 10 is held in contact with the lightly-doped n-type aluminum gallium arsenide layer 5. The n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5. Thus, the electron supply layer 4/5 has the stepped dopant concentration structure.
On the lightly-doped aluminum gallium arsenide layer 5 is epitaxially grown heavily-doped n-type gallium arsenide from which forms the cap layers 8 of 80 nanometers thick are formed. The dopant concentration is 3xc3x971018/cm3 in the heavily-doped n-type gallium arsenide layer. Namely, the heavily-doped n-type gallium arsenide layer is partially etched so as to expose the electron supply layer 4/5 to a recess between the cap layers 8. The gate electrode 10 is held in contact with the exposed portion to the electron supply layer 5. On the other hand, the ohmic electrodes 9 are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
The prior art high electron mobility transistor achieves a large mutual conductance by virtue of the heavily-doped n-type aluminum gallium arsenide layer 4 as well as a high withstand voltage by virtue of the lightly-doped n-type aluminum gallium arsenide layer 5. However, the threshold voltage and, accordingly, the amount of channel current are liable to fluctuate among the products. This is because of the fact that the etchant is liable to partially remove the lightly-doped n-type aluminum gallium arsenide layer 5 during the formation of the recess.
An etching stopper has been proposed as a countermeasure against the problem. The recess is formed by using mixture of citric acid and H2O2 as wet etchant. Upon completion of the fabrication process, the prior art high electron mobility transistor has the structure shown in FIG. 2.
The prior art high electron mobility transistor is fabricated on a semi-insulating substrate 1, which is formed of gallium arsenide. The prior art high electron mobility transistor comprises a buffer layer 2, a channel layer 3, an electron supply layer 4/5, etching stopper layers 7, cap layers 8, ohmic electrodes 9 and a gate electrode 10. Gallium arsenide is epitaxially grown on the semi-insulating substrate 1, and forms a gallium arsenide layer. The gallium arsenide layer serves as the buffer layer 2. On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer 3. Heavily-doped n-type aluminum gallium arsenide, i.e., n+Al0.2Ga0.8As and lightly-doped n-type aluminum gallium arsenide, i.e., nxe2x88x92Al0.2Ga0.8As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly-doped n-type aluminum gallium arsenide layer 5. The dopant concentration is 4xc3x971018/cm3 in the heavily-doped n-type aluminum gallium arsenide layer 4 and 1xc3x971017/cm3 in the lightly-doped n-type aluminum gallium arsenide layer 5. The heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5 form in combination the electron supply layer 4/5. The heavily-doped n-type aluminum gallium arsenide layer 4 is contiguous to the channel layer 3, and the gate electrode 10 is held in contact with the lightly-doped n-type aluminum gallium arsenide layer 5. The n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5. Thus, the electron supply layer 4/5 has the stepped dopant concentration structure.
On the lightly-doped aluminum gallium arsenide layer 5 is grown lightly-doped n-type aluminum gallium arsenide nxe2x88x92Al0.7Ga0.3As which forms a lightly-doped n-type aluminum gallium arsenide layer. The etching stopper layers 7 are formed from the lightly-doped n-type aluminum gallium arsenide layer. Heavily-doped n-type gallium arsenide is epitaxially grown to 80 nanometers thick on the lightly-doped n-type aluminum gallium arsenide layer 7, and forms a heavily-doped n-type gallium arsenide layer. The cap layers 8 are formed from the heavily-doped n-type gallium arsenide layer. The dopant concentration is 3xc3x971018/cm3 in the heavily-doped n-type gallium arsenide layer. The heavily-doped n-type gallium arsenide layer 8 and the lightly-doped aluminum gallium arsenide layer 7 are partially etched so as to expose the electron supply layer 4/5 to a recess between the cap layers 8. The gate electrode 10 is held in contact with the exposed portion of the electron supply layer 5. On the other hand, the ohmic electrodes 9 are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
The lightly-doped n-type Al0.7Ga0.3As layer 7 gives an end point to the wet etchant in the formation of the recess, and prevents the lightly doped Al0.8Ga0.2As layer 5 from the wet etchant. As a result, the electron supply layer 4/5 is constant in thickness, and the electron supply layer 4/5 keeps the threshold constant among products.
However, a problem is encountered in the prior art high electron mobility transistor shown in FIG. 2 in the high source resistance.
It is therefore an important object of the present invention to provide a compound semiconductor device, which is reduced in source resistance without sacrifice of the constant thickness of the active layer.
It is also an important object of the present invention to provide a process for fabricating the compound semiconductor device.
The present inventors contemplated the problem inherent in the prior art high electron mobility transistor shown in FIG. 2, and noticed that the nxe2x88x92Al0.7Ga0.3As etching stopper layers 7 were left between the electron supply layer 5 and the cap layers 8. Aluminum had the large composition ratio in the nxe2x88x92Al0.7Ga0.3As. The aluminum was a large amount of dx center, and the dx centers were not activated with the n-type dopant impurity, i.e., silicon. Even though the silicon was doped in the Al0.7Ga0.3As, a non-ignoreable amount of n-type dopant impurities were invalid, and the lightly-doped Al0.7Ga0.3As layer exhibited high resistivity. The present inventors replaced the lightly-doped nxe2x88x92Al0.7Ga0.3As etching stopper layers 7 with non-doped etching stopper layers. The high electron mobility transistor also exhibited large source resistance. The present inventors concluded that the resistance was to be reduced without deleting the etching stopper layer was required.
To accomplish the object, the present invention proposes to reduce the potential barrier between cap layers and an active layer by using delta-doped layers.
In accordance with one aspect of the present invention, there is provided a compound semiconductor device fabricated on a substrate comprising a multiple-layered structure including an active layer, plural cap layers respectively located over plural portions of the active layer, plural highly-resistive layers formed between the multiple-layered structure and the plural cap layers so as to form a recess located over a part of the multiple-layered structure and between the plural cap layers, plural delta-doped layers formed between the plural highly-resistive layers and the multiple-layered structure for decreasing potential barriers of the plural highly-resistive layers, a first electrode held in contact with the part of the multiple-layered structure for controlling the amount of current flowing through the active layer, and second electrodes respectively formed on the plural cap layers for providing current paths from and to the active layer through the plural cap layers, the plural highly-resistive layers and the plural delta-doped layers.
In accordance with another aspect of the present invention, there is provided a process for fabricating a compound semiconductor device comprising the steps of a) producing a multiple-layered structure having an active layer, a delta-doped layer over the active layer, a highly resistive layer over the delta-doped layer and a highly conductive layer over the delta-doped layer on a semi-insulating substrate, b) removing a part of the highly conductive layer so as to expose a part of the highly resistive layer to a first opening formed between remaining portions of the highly conductive layer serving as plural cap layers, c) removing the part of the highly resistive layer and a part of the delta-doped layer thereunder so as to expose a part of the active layer to a second opening formed between plural delta doped layers respectively overlain by highly resistive layers and d) completing a compound semiconductor device having a first electrode held in contact with the part of the active layer and second electrodes respectively held in contact with the plural cap layers.